This invention relates generally to a process for fabricating semiconductor devices, and more specifically to processes for forming vias in semiconductor devices using self-aligned metal pillars.
Integrated circuits commonly use multi-level metal interconnect as a means for reducing the layout area required for the tens or hundreds of thousands of semiconductor devices that typically form an integrated circuit. This reduction in layout area is possible because the two or more metal layers used in multi-level metal schemes are separated by dielectric layers that allow crisscrossing of the separated metal layers without electrical shorting. Intentional connections between metal layers separated by a dielectric are created by forming small apertures in the dielectric and filling the aperture with a conducting material such as aluminum. These connections are usually made between consecutive metal layers and are known as vias.
As semiconductor device geometries continue to shrink into the submicron range, it is increasingly difficult to maintain planar metal and dielectric surfaces during the formation of multi-level metal interconnect. This lack of planarity can cause several problems. For instance, if the underlying topography coated by a photoresist layer contains abrupt steps due to poor planarity, the photoresist layer's thickness will not be uniform. This can occur, for example, when photoresist is applied to overlie features formed earlier in a semiconductor device process that protrude from the surface of a wafer. Photoresist cannot be applied uniformly over such a topography. This nonuniformity in thickness can lead to some regions of the patterned photoresist layer being inadequately thick to protect underlying features during a later etching step and other regions being excessively thick so that the full thickness of the photoresist layer cannot be exposed due to the depth-of-focus limitations of photolithography at sub-micron dimensions. Also, poor planarity of metal and dielectric layers promotes poor metal step coverage which increases metal sheet-resistance, susceptibility to current-stress stress failure, electromigration problems, and the probability of electrical opens. In addition, poor planarity in underlying metal or dielectric layers formed earlier in a semiconductor device process further increases the difficulty of establishing planarity in overlying metal or dielectric layers formed later in that process.
Another difficulty associated with via formation for multi-level metal interconnect in sub-micron semiconductor devices is the alignment of upper and lower metal layers with an aperture formed in a dielectric for a via. This alignment is difficult because of the small distance between device features in sub-micron devices and the reduced tolerance available for alignment errors. Misalignment of a via relative to connected upper and lower metal layers can lead to reduced device yield, increased via resistance, and poor metal step coverage in the via. For example, in a standard via, misalignment of the via relative to the lower metal layer results in overetching into the dielectric underlying the lower metal layer, thereby increasing the aspect ratio of the via opening and preventing adequate step coverage when later filling the via with metal; the result is a poor contact interface in the via and increased via resistance. Misalignment of an upper metal layer relative to a via results in overetching, or notching, of the lower metal layer; the notched lower metal layer exhibits increased current density and is thus more susceptible to failure from electromigration or current stress.
In many semiconductor devices, the layout dimensions of upper and lower metal layers connecting to vias are extended in the vicinity of the via to form a layout frame, or head, around the via. This is known as framing the via, and the frame provides additional alignment margin such that if partial misalignment of an upper and lower metal layer relative to the intended via location occurs, the actual formed via will still overlie a portion of a lower metal layer or underlie a portion of an upper metal layer. However, an adverse effect of using framed vias in a semiconductor device layout is that the packing density is substantially decreased (or the layout area is substantially increased).
Accordingly, a need existed for a method of forming a via for connecting multi-level interconnect in sub-micron semiconductor devices that improves the surface planarity of formed metal and dielectric layers and reduces problems associated with via misalignment.
It is therefore an object of this invention to provide an improved method for forming a via in a semiconductor device.
It is a further object of this invention to provide an improved method for forming a via that reduces problems associated with via misalignment.
Still another object of this invention is to provide an improved method for forming a via that improves yield and reliability.
A still further object of this invention is to provide an improved method for forming a via which improves step coverage.